There is a current trend towards reducing the supply voltage level of integrated circuits, especially to reduce their electrical consumption. This forces designers of integrated circuits to develop appropriate technologies to reduce the levels of the threshold voltages of transistors so that these transistors operate at a lower voltage with sufficient reliability. Taking as example the prior art 0.25 micron CMOS technology, a sum of the threshold voltages of a P-type transistor (.vertline.Vtp.vertline.=475 mV) and an N-type transistor (Vtn=469 mV) reaches about 900 millivolts. Accordingly, there will be some difficulties in obtaining the operation of a device using this technology at a logic supply voltage of 1 volt or less.
One way of operating an integrated circuit at a low or a very low voltage is to modify the characteristics of certain transistors placed on critical conduction paths. For this purpose, it is possible to use a negative voltage level instead of the zero voltage commonly used. In particular, applying a negative voltage level to a P-type MOS transistor gate makes it more conductive than if a zero voltage were to be applied.
As a result, it is possible to compensate part of the loss due to the threshold voltage of this transistor. It is also possible to apply the negative voltage to a drain of the transistor or to use it to bias a well to appropriately modify a characteristic. For example, modification can be made to the well-substrate voltage of a transistor or in the reduction of the conduction of the transistor. A result of using a negative voltage level is an increased operating range at lower voltages.